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[VHDL-FPGA-Verilog] ParallelSerialMult

Description: 用verilog代码实现了 并行线性序列乘法器，流水线技术实现了乘法操作-Verilog code using a linear sequence of parallel multipliers, pipeline technology to achieve a multiplication operation
Platform: | Size: 2048 | Author: 蒋帅 | Hits:

[Embeded-SCM Develop] cf_fp_mul_p_5_10

Description: verilog浮点乘发器，特定数据结构，指数底为10,利用pipeline-Verilog float by their hair, a specific data structure, the index for the end of October, using pipeline
Platform: | Size: 4096 | Author: 行唐县城 | Hits:

[Embeded-SCM Develop] cf_fp_mul_p_8_23

Description: verilog浮点乘发器，特定数据结构，指数底为10,利用pipeline-Verilog float by their hair, a specific data structure, the index for the end of October, using pipeline
Platform: | Size: 6144 | Author: anmili | Hits:

[VHDL-FPGA-Verilog] cpu_design

Description: FPGA MIPS架构CPU，五段流水线功能，ISE开发，verilog语言，可综合，模拟结果正确，内含设计报告-FPGA MIPS CPU, simple five-stage pipeline function, developed by ISE, using verilog language
Platform: | Size: 2428928 | Author: leo | Hits:

[VHDL-FPGA-Verilog] Elham-Zahraei-Salehi_-Sina-Saharkhiz-(1)

Description: here it is a file which is consist of design of a MIPS pipeline in verilog, it also has test part an it work perfectly. the code is written in good way to understand it easily
Platform: | Size: 150528 | Author: eli | Hits:

[VHDL-FPGA-Verilog] flow_proc

Description: FPGA FLOW verilog流水线把一个复杂的逻辑分成若干个比较简单的块实现，减少信号的逻辑级，提高频率。以芯片面积换取时间，即面积换取频率-FPGA FLOW verilog To a complex pipeline logic is divided into several blocks to achieve a relatively simple, reduce the logic level signal, increasing the frequency. The chip area for time, that area in exchange for frequency
Platform: | Size: 245760 | Author: 网窝囊 | Hits:

[Other] dot_product

Description: 实现矩阵相乘，即点积运算，为VERILOG语言。可以根据自己的需要改变维数，采用了流水线的结构-Achieve matrix multiplication, ie dot product operations, for VERILOG language. You can change the dimension according to their needs, using a pipeline structure
Platform: | Size: 2048 | Author: 桑梓 | Hits:

[VHDL-FPGA-Verilog] fifo_pipeline_booth_multiplier

Description: fifo_pipeline_modified_booth_multiplier一个使用FIFO的Booth乘法器，并且使用了流水线描述方式，本程序给予verilog 语言-fifo_pipeline_modified_booth_multiplier, a booth multiplier using pipeline technology in verilog HDL language
Platform: | Size: 3072 | Author: 谷雨 | Hits:

[VHDL-FPGA-Verilog] pipeline_streamlined_divider

Description: pipeline_streamlined_divider, 一个流水线的除法器，使用Verilog HDL语言编写-pipeline_streamlined_divider， a divider using pipeline technology in verilog HDL language
Platform: | Size: 3072 | Author: 谷雨 | Hits:

[VHDL-FPGA-Verilog] ppv2

Description: pipeline流水线用MIPS实现，用的是verilog。解决流水线的各种冲突。-pipeline pipeline with MIPS implementation, using verilog. Resolve conflicts pipeline.
Platform: | Size: 5018624 | Author: 勿苛刻 | Hits:

[Other] 0340196Lab3

Description: 这是用Verilog语言编写的带有pipeline功能的CPU，适合于学习计算机组织的同学-This is a Verilog language functions CPU with pipeline for students to learn computer organization
Platform: | Size: 484352 | Author: 王倩倩 | Hits:

[Disk Tools] cal_pipeline

Description: 用system verilog 来实习的 1 stage pipeline calculator. It has been successful compiled in Modelsim-System Verilog Calculator
Platform: | Size: 2048 | Author: Jianwei Qiu | Hits:

[VHDL-FPGA-Verilog] liushui

Description: 本程序实现流水线功能，您可根据自己需要更改参数，试用芯片xilinx，用verilog语言编写-This program implements the pipeline, you may be required to change the parameters according to their own try xilinx chip with verilog language
Platform: | Size: 72704 | Author: liyi | Hits:

[VHDL-FPGA-Verilog] mips

Description: Verilog语言开发的基于mips指令集的流水线cpu，只支持部分指令-Verilog language-based development pipeline cpu mips instruction set support only part of the instruction
Platform: | Size: 15360 | Author: DY | Hits:

[VHDL-FPGA-Verilog] mips

Description: 基于mips架构的五级流水线硬件实现。使用verilog-Based on the five-stage pipeline hardware architecture mips
Platform: | Size: 4096 | Author: 毕翔宇 | Hits:

[VHDL-FPGA-Verilog] pipeline_add

Description: pipeline式累加器的verilog代码和testbench文件，已验证-pipeline type accumulator verilog testbench code and documents, verified
Platform: | Size: 4096 | Author: adfadf | Hits:

[VHDL-FPGA-Verilog] pcpu_handle_mem

Description: Verilog实现五级流水线CPU，hazard以及时序功能已经实现。-Realize five-stage pipeline CPU
Platform: | Size: 11389952 | Author: llly | Hits:

[VHDL-FPGA-Verilog] PipelineCPU

Description: 一个用Verilog HDL语言所写的32位MIPS指令系统流水线CPU，含代码工程文件和相关设计说明文档，比较详细。-verilog HDL, 32 MIPS pipeline CPU
Platform: | Size: 3544064 | Author: 刘加东 | Hits:
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